View HYS64T32000KM-37-A_4776433.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

never stop thinking. p r e l i m i nar y hys64t32000[h /k/l]m?[3.7/5]?a hys64t64020[h /k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm ddr2 mdimm data sheet, rev. 0.6, june 2004 memory products
the information in this document is subject to change without notice. edition 2004-06 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. p r e l i m i nar y hys64t32000[h /k/l]m?[3.7/5]?a hys64t64020[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm ddr2 mdimm data sheet, rev. 0.6, june 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a preliminary revision history: rev. 0.6 2004-06 previous revision: rev. 0.5 2004-04 page subjects (major changes since last revision) all added production variants with ?h? instead of ?l? in product type we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm data sheet 5 rev. 0.6, 2004-06 03242004-2cbe-ij2x 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 odt (on die termination) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 electrical characteristics & ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 product type nomenclature (ddr2 drams and dimms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table of contents
preliminary double-data-rate-tw o sdram micro-dimm ddr2 mdimm hys64t32000[h/k/l]m?[3.7/5]?a hys64t64020[h/k/l]m?[3.7/5]?a data sheet 6 rev. 0.6, 2004-06 03242004-2cbe-ij2x 1 overview this chapter gives an overview of the double-data-rate-two sdram micro-dimm product family and describes its main characteristics. 1.1 features 214-pin pc2-4200 and pc2-3200 ddr2 sdram memory modules for use as main memory when installed in systems such as mobile personal computers. 32m 64 and 64m 64 module organisation and 32m 16 chip organisation jedec standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply built with 512mb ddr2 sdrams in p-tfbga-84-2 chipsize packages programmable cas latencies (3, 4 and 5), burst length (8 & 4) and burst type burst refresh, distributed refresh and self refresh all inputs and outputs sstl_1.8 compatible ocd (off-chip driver impedance adjustment) and odt (on-die termination) serial presence detect with e 2 prom micro-dimm dimensions (nominal) : 30 mm high, 54.0 mm wide based on jedec standard reference layouts raw card ?a? & ?b? 2-piece type mezzanine socket with 0,4 mm contact centers 1.2 description the infineon hys64t[3200/6402]0[h/k/l]m? [3.7/5]?a module family are low profile unbuffered micro-dimm modules ?mdimms? with 30,0 mm height based on ddr2 technology. dimms are available as 32m 64 and 64m 64 organisation and density, intended for mounting into 214-pin mezzanine connector sockets. the memory array is designed with 512mb double- data-rate-two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer. table 1 performance product type speed code ?3.7 ?5 units speed grade pc2?4200 4?4?4 pc2?3200 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 60 60 ns
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 7 rev. 0.6, 2004-06 03242004-2cbe-ij2x the compliance code is printed on the module label and provides technical details to the user, e. g. "512mb 2r 16 pc2-4200m-444-11-a0" where "512mb" tells the density in megabytes, "2r 16" means 2 ranks on module built of 16 components, "pc2-4200m" means ddr2 micro-dimm with 4.26 gb/s module bandwidth, "444-11" means cas latency of 4, rcd 1) latency of 4, and rp 2) latency of 4 using jedec spd revision 1.1, and ?a0? means jedec raw card a revision 0. all product types end with a place code, designating the silicon die revision. example: hys72t64000km?5?a, indicating rev. a dies are used for ddr2 sdram components. for all infineon ddr2 module and component nomenclature see chapter 8 of this data sheet. table 2 ordering information product type compliance code description sdram technology hys64t64020km-3.7-a 512mb 2rx16 pc2-4200m-444-11-a0 two ranks 512 mbyte dimm 512 mbit ( 16) hys64t32000km-3.7-a 256mb 1rx16 pc2-4200m-444-11-b0 one rank 256 mbyte dimm hys64t64020km-5-a 512mb 2rx16 pc2-3200m-333-11-a0 two ranks 512 mbyte dimm hys64t32000km-5-a 256mb 1rx16 pc2-3200m-333-11-b0 one rank 256 mbyte dimm hys64t64020hm-3.7-a 512mb 2rx16 pc2-4200m-444-11-a0 two ranks 512 mbyte dimm 512 mbit ( 16) hys64t64020lm-3.7-a 512mb 2rx16 pc2-4200m-444-11-a0 two ranks 512 mbyte dimm hys64t32000hm-3.7-a 256mb 1rx16 pc2-4200m-444-11-b0 one rank 256 mbyte dimm hys64t32000lm-3.7-a 256mb 1rx16 pc2-4200m-444-11-b0 one rank 256 mbyte dimm hys64t64020hm-5-a 512mb 2rx16 pc2-3200m-333-11-a0 two ranks 512 mbyte dimm hys64t64020lm-5-a 512mb 2rx16 pc2-3200m-333-11-a0 two ranks 512 mbyte dimm hys64t32000hm-5-a 256mb 1rx16 pc2-3200m-333-11-b0 one rank 256 mbyte dimm hys64t32000lm-5-a 256mb 1rx16 pc2-3200m-333-11-b0 one rank 256 mbyte dimm 1) rcd: row column delay 2) rp: row precharge table 3 address format dimm density module organization memory ranks # of sdrams # of row/bank/column bits raw card 256 mbyte 32m 64 1 4 13/2/10 b 512 mbyte 64m 64 2 8 13/2/10 a table 4 components on modules 1) 1) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. product type dram components dra m density dram organisation hys64t32000hm 2) hys64t32000lm 2) 2) green product hyb18t512160af 2) 512 mbit 32m 16 hys64t32000km hyb18t512160ac 512 mbit 32m 16 hys64t64020hm 2) hys64t64020lm 2) hyb18t512160af 2) 512 mbit 32m 16 hys64t64020km hyb18t512160ac 512 mbit 32m 16
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 8 rev. 0.6, 2004-06 03242004-2cbe-ij2x 1.3 pin configuration the pin configuration of the ddr2 sdram micro-dimm is listed by function in table 5 (214 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 . table 5 pin configuration of mdimm pin# name pin type buffer type function clock signals 122 ck0 i sstl clock signals 1:0 194 ck1 i sstl 123 ck0 isstl complement clock signals 1:0 195 ck1 isstl 43 cke0 i sstl clock enables note: 2-rank module 147 cke1 i sstl nc nc note: 1-rank module control signals 165 s0 isstl chip select rank 0 62 s1 isstl chip select rank 1 note: 2-rank module nc nc note: 1-rank module 163 ras isstl row address strobe 60 cas isstl column address strobe 56 we isstl write enable address signals 55 ba0 i sstl bank address 1:0 162 ba1 i sstl 161 a0 i sstl address inputs 9:0 159 a1 i sstl 52 a2 i sstl 158 a3 i sstl 51 a4 i sstl 50 a5 i sstl 157 a6 i sstl 48 a7 i sstl 155 a8 i sstl 154 a9 i sstl 54 a10 i sstl address input 10/autoprecharge ap i sstl 47 a11 i sstl address input 11 153 a12 i sstl address input 12
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 9 rev. 0.6, 2004-06 03242004-2cbe-ij2x data signals 3dq0i/osstl data bus 63:0 4dq1i/osstl 9dq2i/osstl 10 dq3 i/o sstl 109 dq4 i/o sstl 110 dq5 i/o sstl 114 dq6 i/o sstl 115 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 117 dq12 i/o sstl 118 dq13 i/o sstl 125 dq14 i/o sstl 126 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 128 dq20 i/o sstl 129 dq21 i/o sstl 133 dq22 i/o sstl 134 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 38 dq26 i/o sstl 39 dq27 i/o sstl 136 dq28 i/o sstl 137 dq29 i/o sstl 142 dq30 i/o sstl 143 dq31 i/o sstl 67 dq32 i/o sstl 68 dq33 i/o sstl 73 dq34 i/o sstl 74 dq35 i/o sstl 174 dq36 i/o sstl 175 dq37 i/o sstl 179 dq38 i/o sstl table 5 pin configuration of mdimm pin# name pin type buffer type function
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 10 rev. 0.6, 2004-06 03242004-2cbe-ij2x 180 dq39 i/o sstl data bus 63:0 76 dq40 i/o sstl 77 dq41 i/o sstl 81 dq42 i/o sstl 82 dq43 i/o sstl 182 dq44 i/o sstl 183 dq45 i/o sstl 188 dq46 i/o sstl 189 dq47 i/o sstl 84 dq48 i/o sstl 85 dq49 i/o sstl 92 dq50 i/o sstl 93 dq51 i/o sstl 191 dq52 i/o sstl 192 dq53 i/o sstl 200 dq54 i/o sstl 201 dq55 i/o sstl 95 dq56 i/o sstl 96 dq57 i/o sstl 101 dq58 i/o sstl 102 dq59 i/o sstl 203 dq60 i/o sstl 204 dq61 i/o sstl 208 dq62 i/o sstl 209 dq63 i/o sstl 112 dm0 i sstl data masks 7:0 note: see block diagram for corresponding dq m signals 120 dm1 i sstl 131 dm2 i sstl 36 dm3 i sstl 177 dm4 i sstl 79 dm5 i sstl 90 dm6 i sstl 206 dm7 i sstl table 5 pin configuration of mdimm pin# name pin type buffer type function
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 11 rev. 0.6, 2004-06 03242004-2cbe-ij2x 7dqs0i/osstl data strobes 7:0 note: see block diagram for corresponding dqs signals 6dqs0 i/o sstl 19 dqs1 i/o sstl 18 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 140 dqs3 i/o sstl 139 dqs3 i/o sstl 71 dqs4 i/o sstl 70 dqs4 i/o sstl 186 dqs5 i/o sstl 185 dqs5 i/o sstl 198 dqs6 i/o sstl 197 dqs6 i/o sstl 99 dqs7 i/o sstl 98 dqs7 i/o sstl eeprom 105 scl i cmos serial presence detect (spd) clock input 104 sda i/o od spd data input/output 211 sa0 i cmos spd address 1:0 213 sa1 i cmos power supplies 1 v ref ai ? i/o reference voltage 42, 45, 49, 53, 57, 61, 64, 146, 149, 152, 156, 160, 164, 168, 171 v dd pwr ? power supply 107 v ddspd pwr ? eeprom power supply 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 37, 40, 66, 69, 72, 75, 78, 80, 83, 86, 89, 91, 94, 97, 100, 103, 108, 111, 113, 116, 119, 121, 124, 127, 130, 132, 135, 138, 141, 144, 173, 176, 178, 181, 184, 187, 190, 193, 196, 205, 199, 202, 207, 210 v ss gnd ? ground plane other pins 166 odt0 on-die termination control 1:0 note: 2-rank module 63 odt1 nc note: 1-rank module 15, 16, 41, 44, 46, 58, 59, 65, 87, 88, 106, 145, 148, 150, 151, 167, 169, 170, 172, 212, 214 nc nc ? not connected note: pins not connected on infineon mdimms table 5 pin configuration of mdimm pin# name pin type buffer type function
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 12 rev. 0.6, 2004-06 03242004-2cbe-ij2x table 6 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 7 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_1.8) cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or.
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 13 rev. 0.6, 2004-06 03242004-2cbe-ij2x figure 1 pin configuration for two-piece mezzanine socket on mdimm (214 pins) v ss dq5 dm0 dq6 v ss dq13 dm1 ck0 v ss dq15 dq20 v ss v ss dq23 dq28 v ss dqs3 dq30 v ss v dd nc nc v dd a9 v dd a3 v dd ba1 v dd odt0 v dd nc nc dq36 v ss v ss dq39 dq44 v ss dqs5 dq46 v ss dq53 ck1 v ss dqs6 dq54 v ss dq61 dm7 dq62 v ss nc nc dq10 v ss dq17 dqs2 v ss dq19 dq24 v ss v ss dq27 nc cke0 v dd a11 v dd a4 v dd ba0 v dd nc v dd odt1 nc dq32 v ss dqs4 dq34 v ss dq41 dm5 dq42 v ss dq49 nc v ss v ss dq51 dq56 v ss dqs7 dq58 v ss scl v ddspd pin 001 pin 003 pin 005 pin 007 pin 009 pin 011 pin 013 pin 015 pin 017 pin 019 - - - - - - - - - - pin 002 pin 004 pin 006 pin 008 pin 010 pin 012 pin 014 pin 016 pin 018 pin 020 - - - - - - - - - - v ref dq0 v ss dqs0 dq2 v ss dq9 nc v ss dqs1 dq1 dqs0 v ss dq3 dq8 v ss nc dqs1 v ss v ss pin 022 pin 024 pin 026 pin 028 pin 030 pin 032 pin 034 pin 036 pin 038 pin 040 pin 042 pin 044 pin 046 pin 048 pin 050 pin 052 pin 054 pin 056 pin 058 pin 060 pin 062 pin 064 pin 066 pin 068 pin 070 pin 072 pin 074 pin 076 pin 078 pin 080 pin 082 pin 084 pin 086 pin 088 pin 090 pin 092 pin 094 pin 096 pin 098 pin 100 pin 102 pin 104 pin 106 dq11 dq16 v ss dqs2 dq18 v ss dq25 dm3 dq26 v ss v dd nc nc/ba2 a7 a5 a2 a10/ap we nc cas s1 v dd v ss dq33 dqs4 v ss dq35 dq40 v ss v ss dq43 dq48 v ss nc dm6 dq50 v ss dq57 dqs7 v ss dq59 sda nc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 021 pin 023 pin 025 pin 027 pin 029 pin 031 pin 033 pin 035 pin 037 pin 039 pin 041 pin 043 pin 045 pin 047 pin 049 pin 051 pin 053 pin 055 pin 057 pin 059 pin 061 pin 063 pin 065 pin 067 pin 069 pin 071 pin 073 pin 075 pin 077 pin 079 pin 081 pin 083 pin 085 pin 087 pin 089 pin 091 pin 093 pin 095 pin 097 pin 099 pin 101 pin 103 pin 105 pin 107 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 108 pin 110 pin 112 pin 114 pin 116 pin 118 pin 120 pin 122 pin 124 pin 126 - - - - - - - - - - pin 109 pin 111 pin 113 pin 115 pin 117 pin 119 pin 121 pin 123 pin 125 pin 127 - - - - - - - - - - v ss v ss dq7 dq12 v ss v ss ck0 dq14 v ss dq4 pin 129 pin 131 pin 133 pin 135 pin 137 pin 139 pin 141 pin 143 pin 145 pin 147 pin 149 pin 151 pin 153 pin 155 pin 157 pin 159 pin 161 pin 163 pin 165 pin 167 pin 169 pin 171 pin 173 pin 175 pin 177 pin 179 pin 181 pin 183 pin 185 pin 187 pin 189 pin 191 pin 193 pin 195 pin 197 pin 199 pin 201 pin 203 pin 205 pin 207 pin 209 pin 211 pin 213 dq21 dm2 dq22 v ss dq29 dqs3 v ss dq31 nc cke1 v dd nc a12 a8 a6 a1 a0 ras s0 nc nc v dd v ss dq37 dm4 dq38 v ss dq45 dqs5 v ss dq47 dq52 v ss ck1 dqs6 v ss dqs5 dq60 v ss v ss dq63 sa0 sa1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 128 pin 130 pin 132 pin 134 pin 136 pin 138 pin 140 pin 142 pin 144 pin 146 pin 148 pin 150 pin 152 pin 154 pin 156 pin 158 pin 160 pin 162 pin 164 pin 166 pin 168 pin 170 pin 172 pin 174 pin 176 pin 178 pin 180 pin 182 pin 184 pin 186 pin 188 pin 190 pin 192 pin 194 pin 196 pin 198 pin 200 pin 202 pin 204 pin 206 pin 208 pin 210 pin 212 pin 214 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm overview data sheet 14 rev. 0.6, 2004-06 03242004-2cbe-ij2x table 8 input/output functional description symbol type polarity function ck[1:0], ck [1:0] i cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] i active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s[1:0] iactive low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0; rank 1 is selected by s1. ras , cas , we iactive low when sampled at the cross point of the rising edge of ck,and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. ba[1:0] i ? selects internal sdram memory bank odt[1:0] i active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. a[9:0], a10/ap, a[12:11] i ? during a bank activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[1:0] to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba[1:0] inputs. if ap is low, then ba[1:0] are used to define which bank to precharge. dq[63:0] i/o ? data input/output pins dm[7:0] i active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs[7:0], dqs [7:0] i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ? to 10 k ? resistor and ddr2 sdram mode registers programmed appropriately. v dd , v ddspd , v ss supply ? power supplies for core, i/o, serial presence detect, and ground for the module. sda i/o ? this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to to v ddspd on the motherboard to act as a pull-up. scl i ? this signal is used to clock data into and out of the spd eeprom. sa[1:0] i ? address pins used to select the serial presence detect base address.
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm block diagrams data sheet 15 rev. 0.6, 2004-06 03242004-2cbe-ij2x 2 block diagrams figure 2 block diagram raw card a (x64, 2 ranks, x16) notes 1. dq, dqs, dm resistors are 22 ? 5% 2. s0, s1 , ban, an, ras , cas , we, odto, odt1, ckeo, cke1 resistors are 3 ? 5% mpbt0010 dm0 dqs0 dqs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm1 dqs1 dqs1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d0 dm2 dqs2 dqs2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm3 dqs3 dqs3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d2 dm4 dqs4 dqs4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm5 dqs5 dqs5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d6 d7 dm6 dqs6 dqs6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm7 dqs7 dqs7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 s0 s1 d4 d1 d5 d3 ba0 - ba1 a0 - an ras cas we cke0 cke1 odt0 odt1 ck0 ck0 ck1 ck1 4 loads 4 loads ba0 - ba1: sdrams d0 - d7 a0 - an: sdrams d0 - d7 ras: sdrams d0 - d7 cas: sdrams d0 - d7 we: sdrams d0 - d7 cke0: sdrams d0 - d3 cke1: sdrams d4 - d7 odt0: sdrams d0 - d3 odt1: sdrams d4 - d7 scl sda sa0 sa1 v dd : spd eeprom e0 v dd / v ddq : sdrams d0 - d7 v ref : sdrams d0 - d7 v ss : sdrams d0 - d7 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldm ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 e0 v dd,spd v dd / v ddq v ref v ss scl sda a0 a1 a2 wp vss
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm block diagrams data sheet 16 rev. 0.6, 2004-06 03242004-2cbe-ij2x figure 3 block diagram raw card b (x64, 1 rank, x16) notes 1. dq, dqs, dm resistors are 22 ? 5% 2. s0, ban, an, ras , cas , we, odto, ckeo resistors are 3 ? 5% 3. load matching capacitors on ba0 - ba1, a0 - an, ras , cas , we , with 8 pf 0.5pf mpbt0020 dm0 dqs0 dqs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm1 dqs1 dqs1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d0 dm2 dqs2 dqs2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm3 dqs3 dqs3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d1 dm4 dqs4 dqs4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm5 dqs5 dqs5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d2 d3 dm6 dqs6 dqs6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm7 dqs7 dqs7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 s0 e0 ldm cs ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ba0 - ba1 a0 - an ras cas we cke: sdrams d0 - d3 odt: sdrams d0 - d3 cke0 odt0 v ss : sdrams d0 - d3 v ss v dd : spd eeprom e0 v dd / v ddq : sdrams d0 - d3 v ref : sdrams d0 - d3 v ss : sdrams d0 - d3 ba0 - ba1: sdrams d0 - d3 a0 - an: sdrams d0 - d3 ras: sdrams d0 - d3 cas: sdrams d0 - d3 we: sdrams d0 - d3 ck0 ck0 ck1 ck1 scl sda sa0 sa1 v dd,spd v dd / v ddq v ref v ss 2 loads 2 loads scl sda a0 a1 a2 wp vss
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm electrical characteristics data sheet 17 rev. 0.6, 2004-06 03242004-2cbe-ij2x 3 electrical characteristics 3.1 operating conditions table 9 absolute maximum ratings parameter symbol values unit note/test condition min. max. voltage on any pins relative to v ss v in , v out ? 0.5 2.3 v 1) 1) stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability voltage on v dd relative to v ss v dd ? 1.0 2.3 v 1) voltage on v ddq relative to v ss v ddq ? 0.5 2.3 v 1) storage humidity (without condensation) h stg 595% 1) table 10 operating conditions parameter symbol values unit notes min. max. operating temperature (ambient) t opr 0+65 c dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. for measurement conditions, please refer to the jedec document jesd51-2 2) within the dram component case temperature range all dram specifications will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) self-refresh period is hard-coded in the drams and therefore it is imperative that the system ensures the dram is below 85 c case temperature before initiating self-refresh operation. storage temperature t stg ? 50 +100 c barometric pressure (operating & storage) 105 69 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % table 11 supply voltage levels and dc operating conditions parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 1.7 1.8 1.9 v ? output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih (dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc) ? 0.30 ? v ref ?0.125 v
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm i dd specifications and conditions data sheet 18 rev. 0.6, 2004-06 03242004-2cbe-ij2x 4 i dd specifications and conditions table 12 i dd measurement conditions 1)2) parameter symbol operating current 0 one bank active - precharge; t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching . i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , t rcd = t rcdmin. ,al = 0, cl = cl min .; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge power-down current other control and address inputs are stable, data bus inputs are floating . i dd2p precharge standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are switching, data bus inputs are switching. i dd2n precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit); i dd3p(0) active power-down current all banks open; tck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin .; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ckmin ., refresh command every t rfc = t rfcmin. interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ckmin. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm i dd specifications and conditions data sheet 19 rev. 0.6, 2004-06 03242004-2cbe-ij2x self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. reset = low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) for details and notes see the relevant infineon component data sheet table 13 i dd specification product type hys64t32000hm-5-a hys64t32000lm-5-a hys64t32000km-5-a hys64t32000hm-3.7-a hys64t32000lm-3.7-a hys64t32000km-3.7-a hys64t64020hm-5-a hys64t64020lm-5-a hys64t64020km-5-a hys64t64020hm-3.7-a hys64t64020lm-3.7-a hys64t64020km-3.7-a unit notes organization 256 mb 256 mb 512 mb 512 mb 1 rank 1 rank 2 ranks 2 ranks 64 64 64 64 symbol max. max. max. max. i dd0 280 320 296 336 ma 1)2) 1) calculated values from component data. odt disabled. i dd1 , i dd4r , and i dd7 are defined with the outputs disabled. 2) for 2-rank modules only: the other rank is in i dd2p precharge power-down standby current mode i dd1 300 360 316 376 ma 1)2) i dd2p 16 16 32 32 ma 1) 3) 3) for 2-rank modules only: both ranks are in the same i dd mode i dd2n 128 160 256 320 ma 1) 3) i dd2q 100 120 200 240 ma 1) 3) i dd3p(0) 52 64 104 128 ma 1) 3) i dd3p(1) 20 20 40 40 ma 1) 3) i dd3n 140 160 280 320 ma 1) 3) i dd4r 340 400 356 416 ma 1)2) i dd4w 360 440 376 456 ma 1)2) i dd5b 480 520 496 536 ma 1)2) i dd5d 24 24 40 40 ma 1) 3) i dd6 16 16 32 32 ma 1) 3) i dd7 840 880 856 896 ma 1)2) table 12 i dd measurement conditions 1)2) (cont?d) parameter symbol
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm i dd specifications and conditions data sheet 20 rev. 0.6, 2004-06 03242004-2cbe-ij2x 4.1 i dd test conditions for testing the i dd parameters, the timing parameters as in table 14 are used. 4.2 odt (on die termination) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a[6,2] in the emrs(1) a ?weak? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time. note: for power consumption calculations the odt duty cycle has to be taken into account table 14 idd measurement test condition parameter symbol -3.7 -5 unit pc2-4200-4-4-4 pc2-3200-3-3-3 cas latency cl min 43 t ck clock cycle time t ckmin 3.75 5 ns active to read or write delay t rcdmin 15 15 ns active to active / auto-refresh command period t rcmin 60 60 ns active bank a to active bank b command delay t rrdmin 10 10 ns active to precharge command t rasmin 45 45 ns precharge command period t rpmin 15 15 ns auto-refresh to active / auto-refresh command period t rfcmin 105 105 ns average periodic refresh interval t refi 7.8 7.8 s table 15 odt current per terminated pin parameter symbol min. typ. max. unit emrs(1) state enabled odt current per dq odt is high; data bus inputs are floating i odto 5 6 7.5 ma/dq a6 = 0, a2 = 1 2.5 3 3.75 ma/dq a6 = 1, a2 = 0 active odt current per dq odt is high; worst case of data bus inputs are stable or switching. i odtt 10 12 15 ma/dq a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm electrical characteristics & ac timings data sheet 21 rev. 0.6, 2004-06 03242004-2cbe-ij2x 5 electrical characteristics & ac timings table 16 ac timing - absolute specifications ? 5/ ? 3.7 1) parameter symbol ? 3.7 ? 5 unit notes pc2-4200m pc2-3200m min. max. min. max. dq output access time from ck/ck t ac -500 +500 ? 600 + 600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck clock cycle time t ck3 5000 8000 5000 8000 ps 2) t ck4 3750 8000 5000 8000 ps 3) cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ? t is + t ck + t ih ?ns dq and dm input hold time t dh 225 ? 275 ? ps dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck/ck t dqsck ? 450 + 450 ? 500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ? 350 ps write command to 1st dqs latching transition t dqss wl - 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time t ds 100 ? 150 ? ps dqs falling edge hold time from clk (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to clk setup time (write cycle) t dss 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch ) t ck data-out high-impedance time from ck/ck t hz ? t acmax ? t acmax ps address and control input hold time t ih 375 ? 475 ? ps control and addr. input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck address and control input setup time t is 250 ? 350 ? ps dq low-impedance from ck / ck t lz(dq) 2 t acmin t acmax 2 t acmin t acmax ps dqs low-impedance from ck / ck t lz(dqs) t acmin t acmax t acmin t acmax ps mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 0 12 0 12 ns
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm electrical characteristics & ac timings data sheet 22 rev. 0.6, 2004-06 03242004-2cbe-ij2x data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ? t ck data hold skew factor t qhs ? 400 ? 450 ps active to precharge command t ras 45 70000 45 70000 ns active to active/auto-refresh command period t rc 60 ? 60 ? ns active to read or write delay (with and without auto-precharge) delay t rcd 15 ? 15 ? ns average periodic refresh interval t refi ? 7.8 ? 7.8 s 4) ? 3.9 ? 3.9 s 5) auto-refresh to active/auto-refresh command period t rfc 105 ? 105 ? ns precharge command period t rp 15 ? 15 ? ns read preamble t rpre 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.40 0.60 0.40 0.60 t ck active bank a to active bank b command t rrd 10 ? 10 ? ns internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.25 ? 0.25 ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck write recovery time t wr 15 ? 15 ? ns internal write to read command delay t wtr 7.5 ? 10 ? ns exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck exit active power-down mode to read command (slew exit, lower power) t xards 6 ? al ? 6 ? al ? t ck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc + 10 ? t rfc + 10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) for details and notes see the relevant infineon component datasheet 2) cl = 3 3) cl = 4 & 5 4) 0c t case 85 c 5) 85 c < t case 95 c table 16 ac timing - absolute specifications ? 5/ ? 3.7 1) parameter symbol ? 3.7 ? 5 unit notes pc2-4200m pc2-3200m min. max. min. max.
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm electrical characteristics & ac timings data sheet 23 rev. 0.6, 2004-06 03242004-2cbe-ij2x table 17 odt ac electrical characteristics and operating conditions (all speed bins) symbol parameter / condition min. max. unit t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac(min) t ac(max) + 1 ns ns t aonpd odt turn-on (power-down modes) t ac(min) + 2 ns 2 t ck + t ac(max) + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac(min) t ac(max) + 0.6 ns ns t aofpd odt turn-off delay (power-down modes) t ac(min) + 2 ns 2.5 t ck + t ac(max) + 1 ns ns t anpd odt to power down mode entry latency 3? t ck t axpd odt power down exit latency 8 ? t ck
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm spd codes data sheet 24 rev. 0.6, 2004-06 03242004-2cbe-ij2x 6 spd codes table 18 spd codes for pc2-4200m and pc2-3200m product type hys64t64020lm?3.7?a hys64t64020km?3.7?a hys64t64020hm?3.7?a hys64t32000lm?3.7?a hys64t32000km?3.7?a hys64t32000hm?3.7?a hys64t64020lm?5?a hys64t64020km?5?a hys64t64020hm?5?a hys64t32000lm?5?a hys64t32000km?5?a hys64t32000hm?5?a organization 512 mbyte 256 mbyte 512 mb 256 mb 64 64 64 64 2 ranks ( 16) 1 rank ( 16) 2 ranks ( 16) 1 rank ( 16) label code pc2-4200m-444 pc2-4200m-444 pc2-3200m-333 pc2-3200m-333 jedec spd revision rev 1.1 rev 1.1 rev 1.1 rev 1.1 byte# description hex hex hex hex hex hex hex hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 80 80 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 08 08 08 08 08 08 08 2 memory type (ddr = 07h) 080808080808080808080808 3 number of row addresses 0d0d0d0d0d0d0d0d0d0d0d0d 4 number of column addresses0a0a0a0a0a0a0a0a0a0a0a0a 5 number of dimm ranks 616161606060616161606060 6 data width 404040404040404040404040 7 not used 00 00 00 00 00 00 00 00 00 00 00 00 8 interface voltage levels 05 05 05 05 05 05 05 05 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 3d 3d 50 50 50 50 50 50 10 t ac sdram @ clmax (byte 18) [ns] 50 50 50 50 50 50 60 60 60 60 60 60 11 error correction support (non- / ecc) 00 00 00 00 00 00 00 00 00 00 00 00 12 refresh rate/type 828282828282828282828282 13 primary sdram width 101010101010101010101010 14 error checking sdram width000000000000000000000000 15 not used 00 00 00 00 00 00 00 00 00 00 00 00 16 burst length supported 0c0c0c0c0c0c0c0c0c0c0c0c 17 number of banks on sdram device 04 04 04 04 04 04 04 04 04 04 04 04 18 cas latency 38 38 38 38 38 38 38 38 38 38 38 38 19 not used 00 00 00 00 00 00 00 00 00 00 00 00 20 dimm type information 080808080808080808080808 21 dimm attributes 00 00 00 00 00 00 00 00 00 00 00 00
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm spd codes data sheet 25 rev. 0.6, 2004-06 03242004-2cbe-ij2x 22 component attributes 01 01 01 01 01 01 01 01 01 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 3d 3d 50 50 50 50 50 50 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 50 60 60 60 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 50 50 50 50 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 60 60 60 60 60 60 60 60 27 t rpmin [ns] 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 28 t rrdmin [ns] 28 28 28 28 28 28 28 28 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 30 t rasmin [ns] 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 31 module density per rank 40 40 40 40 40 40 40 40 40 40 40 40 32 t as , t cs [ns] 25 25 25 25 25 25 35 35 35 35 35 35 33 t ah , t ch [ns] 37 37 37 37 37 37 47 47 47 47 47 47 34 t ds [ns] 10 10 10 10 10 10 15 15 15 15 15 15 35 t dh [ns] 22 22 22 22 22 22 27 27 27 27 27 27 36 t wr [ns] 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 37 t wtr [ns] 1e 1e 1e 1e 1e 1e 28 28 28 28 28 28 38 t rtp [ns] 1e 1e 1e 1e 1e 1e 1e 1e 1e 1e 1e 1e 39 analysis characteristics 000000000000000000000000 40 t rc and t rfc extension 000000000000000000000000 41 t rcmin [ns] 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 3c 42 t rfcmin [ns] 69 69 69 69 69 69 69 69 69 69 69 69 43 t ckmax [ns] 80 80 80 80 80 80 80 80 80 80 80 80 44 t dqsqmax [ns] 1e 1e 1e 1e 1e 1e 23 23 23 23 23 23 45 t qhsmax [ns] 28 28 28 28 28 28 2d 2d 2d 2d 2d 2d 46 pll relock time 00 00 00 00 00 00 00 00 00 00 00 00 47 tc(max) delta / dt4r4w delta535353535353515151515151 48 psi(t-a) dram 727272727272727272727272 49 dt0 525252525252424242424242 table 18 spd codes for pc2-4200m and pc2-3200m product type hys64t64020lm?3.7?a hys64t64020km?3.7?a hys64t64020hm?3.7?a hys64t32000lm?3.7?a hys64t32000km?3.7?a hys64t32000hm?3.7?a hys64t64020lm?5?a hys64t64020km?5?a hys64t64020hm?5?a hys64t32000lm?5?a hys64t32000km?5?a hys64t32000hm?5?a organization 512 mbyte 256 mbyte 512 mb 256 mb 64 64 64 64 2 ranks ( 16) 1 rank ( 16) 2 ranks ( 16) 1 rank ( 16) label code pc2-4200m-444 pc2-4200m-444 pc2-3200m-333 pc2-3200m-333 jedec spd revision rev 1.1 rev 1.1 rev 1.1 rev 1.1 byte# description hex hex hex hex hex hex hex hex hex hex hex hex
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm spd codes data sheet 26 rev. 0.6, 2004-06 03242004-2cbe-ij2x 50 dt2n (udimm) or dt2q (rdimm) 2b 2b 2b 2b 2b 2b 23 23 23 23 23 23 51 dt2p 1d 1d 1d 1d 1d 1d 1d 1d 1d 1d 1d 1d 52 dt3n 1d 1d 1d 1d 1d 1d 19 19 19 19 19 19 53 dt3pfast 23 23 23 23 23 23 1c 1c 1c 1c 1c 1c 54 dt3pslow 16 16 16 16 16 16 16 16 16 16 16 16 55 dt4r / dt4r4w sign 36 36 36 36 36 36 2e 2e 2e 2e 2e 2e 56 dt5b 1c 1c 1c 1c 1c 1c 1a 1a 1a 1a 1a 1a 57 dt7 3030303030302d2d2d2d2d2d 58 psi(ca) pll 000000000000000000000000 59 psi(ca) reg 000000000000000000000000 60 dtpll 000000000000000000000000 61 dtreg / toggle rate 00 00 00 00 00 00 00 00 00 00 00 00 62 spd revision 11 11 11 11 11 11 11 11 11 11 11 11 63 checksum of byte 0-62 c0 c0 c0 bf bf bf 12 12 12 11 11 11 64 jedec id code of infineon (1)c1c1c1c1c1c1c1c1c1c1c1c1 65 jedec id code of infineon (2)000000000000000000000000 66 jedec id code of infineon (3)000000000000000000000000 67 jedec id code of infineon (4)000000000000000000000000 68 jedec id code of infineon (5)000000000000000000000000 69 jedec id code of infineon (6)000000000000000000000000 70 jedec id code of infineon (7)000000000000000000000000 71 jedec id code of infineon (8)000000000000000000000000 72 module manufacturer location xx xx xx xx xx xx xx xx xx xx xx xx 73 product type, char 1 363636363636363636363636 74 product type, char 2 343434343434343434343434 75 product type, char 3 545454545454545454545454 76 product type, char 4 363636333333363636333333 table 18 spd codes for pc2-4200m and pc2-3200m product type hys64t64020lm?3.7?a hys64t64020km?3.7?a hys64t64020hm?3.7?a hys64t32000lm?3.7?a hys64t32000km?3.7?a hys64t32000hm?3.7?a hys64t64020lm?5?a hys64t64020km?5?a hys64t64020hm?5?a hys64t32000lm?5?a hys64t32000km?5?a hys64t32000hm?5?a organization 512 mbyte 256 mbyte 512 mb 256 mb 64 64 64 64 2 ranks ( 16) 1 rank ( 16) 2 ranks ( 16) 1 rank ( 16) label code pc2-4200m-444 pc2-4200m-444 pc2-3200m-333 pc2-3200m-333 jedec spd revision rev 1.1 rev 1.1 rev 1.1 rev 1.1 byte# description hex hex hex hex hex hex hex hex hex hex hex hex
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm spd codes data sheet 27 rev. 0.6, 2004-06 03242004-2cbe-ij2x 77 product type, char 5 343434323232343434323232 78 product type, char 6 303030303030303030303030 79 product type, char 7 323232303030323232303030 80 product type, char 8 303030303030303030303030 81 product type, char 9 4c 4b 48 4c 4b 48 4c 4b 48 4c 4b 48 82 product type, char 10 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d 4d 83 product type, char 11 33 33 33 33 33 33 35 35 35 35 35 35 84 product type, char 12 2e 2e 2e 2e 2e 2e 41 41 41 41 41 41 85 product type, char 13 37 37 37 37 37 37 20 20 20 20 20 20 86 product type, char 14 41 41 41 41 41 41 20 20 20 20 20 20 87 product type, char 15 20 20 20 20 20 20 20 20 20 20 20 20 88 product type, char 16 20 20 20 20 20 20 20 20 20 20 20 20 89 product type, char 17 20 20 20 20 20 20 20 20 20 20 20 20 90 product type, char 18 20 20 20 20 20 20 20 20 20 20 20 20 91 module revision code 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 0x 92 test program revision code xx xx xx xx xx xx xx xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx xx xx xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx xx xx xx xx xx xx xx 95 module serial number (1) xx xx xx xx xx xx xx xx xx xx xx xx 96 module serial number (2) xx xx xx xx xx xx xx xx xx xx xx xx 97 module serial number (3) xx xx xx xx xx xx xx xx xx xx xx xx 98 module serial number (4) xx xx xx xx xx xx xx xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 00 00 00 00 00 00 00 128- 255 blank ffffffffffffffffffffffff table 18 spd codes for pc2-4200m and pc2-3200m product type hys64t64020lm?3.7?a hys64t64020km?3.7?a hys64t64020hm?3.7?a hys64t32000lm?3.7?a hys64t32000km?3.7?a hys64t32000hm?3.7?a hys64t64020lm?5?a hys64t64020km?5?a hys64t64020hm?5?a hys64t32000lm?5?a hys64t32000km?5?a hys64t32000hm?5?a organization 512 mbyte 256 mbyte 512 mb 256 mb 64 64 64 64 2 ranks ( 16) 1 rank ( 16) 2 ranks ( 16) 1 rank ( 16) label code pc2-4200m-444 pc2-4200m-444 pc2-3200m-333 pc2-3200m-333 jedec spd revision rev 1.1 rev 1.1 rev 1.1 rev 1.1 byte# description hex hex hex hex hex hex hex hex hex hex hex hex
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm package outlines data sheet 32 rev. 0.6, 2004-06 03242004-2cbe-ij2x 7 package outlines figure 4 pcb raw card a component placement l-dim-214-1 30 2.6 0.1 0.2 2.3 0.62 54 b gld09638 2.9 a 0.1 d 0.8 0.08 3.8 max. 106 x 0.4 = 42.4 0.15 0.15 0.03 0.4 43.38 0.02 (44.72) burnished, no burr allowed 0.4 0.26 0.02 0.06 e cd 107x detail of contacts a-a contact area 1.3 0.02 b-b 1.65 -0.25 -0.04 1.08 (2.43) (3.44) 107 214 1 108 4.3 0.1 c 0.1 c m b m e 0.1 m ab m b b a a c
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm package outlines data sheet 33 rev. 0.6, 2004-06 03242004-2cbe-ij2x figure 5 pcb raw card b component placement l-dim-214-2 30 2.6 0.1 0.2 2.3 0.62 54 b gld09668 2.9 a d 2.34 max. 106 x 0.4 = 42.4 0.15 0.15 0.03 0.4 43.38 0.02 (44.72) burnished, no burr allowed 0.4 0.26 0.02 0.06 e cd 107x detail of contacts a-a contact area 1.3 0.02 b-b 1.65 -0.25 -0.04 1.08 (2.43) (3.44) 107 214 1 108 4.3 0.1 c 0.1 c m b m e 0.1 m ab m b b a a 0.08 0.8 0.1 c
preliminary hys64t[3200/6402]0[h/k/l]m?[3.7/5]?a double-data-rate-two sdram micro-dimm product type nomenclature (ddr2 drams and dimms) data sheet 34 rev. 0.6, 2004-06 03242004-2cbe-ij2x 8 product type nomenclature (ddr2 drams and dimms) infineon?s nomenclature uses simple coding combined with some propriatory coding. table 20 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 21 and for components in table 22 . table 20 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys 64 t 64 020km?5?a ddr2 dram hyb 18 t 512 16 0 a c ?5 table 21 ddr2 dimm nomenclature field description values coding 1 infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology tddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 5raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type s s o-dimm m m icro-dimm r r egistered u u nbuffered 10 speed grade ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. table 22 ddr2 dram nomenclature field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status cfbga, lead-containing f fbga, lead-free 10 speed grade ?3.7 ddr2-533 ?5 ddr2-400 11 n/a for components
published by infineon technologies ag www.infineon.com

▲Up To Search▲

Price & Availability of HYS64T32000KM-37-A

	To Download HYS64T32000KM-37-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .